(1.) Field of the Invention
This invention relates generally to digital audio COder-DECoders (CODECs) and relates more specifically to synchronization of a master clock with digital audio signals coming from separate clock domains.
(2.) Description of the Prior Art
Digital audio CODECs typically use a stable master clock as a reference and a phase-locked loop (PLL) to generate the frequencies required for processing the audio data. When used in slave mode, these devices may also be required to maintain synchronization with digital audio signals coming from a separate clock domain, These signals will not be synchronous to the master clock and they may also drift with respect to the master clock. In a complex system with a multiplicity of data sources, the signal frequencies may also change depending on the source. The slave device must therefore be capable of tracking a range of incoming data streams so that audio signal samples are not lost.
Current systems require knowledge of the incoming audio data rate so that an appropriate “gearing ratio” can be selected. This requires some form of handover protocol when switching between audio sources and precludes either switching between audio sources on the fly or switching to an unknown audio source.
It is a challenge for the designers of CODECs to achieve systems capable to automatically detecting a change in data-rate, selecting the correct gearing ratio, and re-establishing synchronization with the new audio source,
There are known patents or patent publications dealing with synchronization with digital audio/video sources.
U.S. Patent Publication (US 2008/0198958 to Shin) proposes an apparatus and method for compensating for a phase jump of a reference signal in a digital Phase-Locked Loop (PLL)/Frequency-Locked Loop (FLL). The apparatus includes a phase discriminator for comparing a phase of an external clock signal (i.e., the reference signal) with a phase of an internal clock signal to determine a phase difference between the two signals, a phase jump compensator, and for correcting the phase difference by using a phase jump correction value obtained in the estimation process, and a Low Pass Filter (LPF) for filtering a high-frequency component of the corrected phase difference.
U.S. Pat. No. 7,499,106 to Gudmunson et al. discloses a method and system for synchronizing video information derived from an asynchronously sampled video signal providing a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the source video clock frequency is computed via an all digital phase-lock loop (ADPLL) and either a video clock is generated from the ratio by another PLL, a number to clock converter or the ratio is used directly to provide digital synchronization information to downstream processing blocks. A sample rate converter (SRC) is provided in an interpolator that either acts as a sample position corrector at the same line rate as the received video, or by introducing an offset in the ADPLL, the video data can be converted to another line rate via the SRC.
U.S. Pat. No. 5,790,615 to Beale et al. describes a digital phase-lock loop network that provides input and output clock signals to a digital data receiving system generally, and particularly to a data buffer contained therein. The digital phase-lock loop network provides bit-clock synchronization using a fixed input clock and an output clock having a variable frequency that is adjusted to correspond to the average input rate of the data samples into the data buffer. The digital phase-lock loop network allows the data buffer to be operated as a temporary storage device maintaining a nominal number of data samples therein at all times by avoiding any overflow and underflow data handling conditions that may otherwise cause loss of data. The digital phase-lock loop network of the present invention is particularly suited for the Eureka-147 system, which has become a worldwide standard for digital audio broadcasting (DAB) technology.
Furthermore U.S. Patent Publication (US 2008/0075152 to Melanson) teaches a hybrid analog/digital phase-lock loop with high-level event synchronization providing a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level and synchronizing the output clock to high-level events. A numerically-controlled analog oscillator provides a clock output and a counter divides the frequency of the clock output to provide input to a digital phase-frequency detector for detecting an on-going phase-frequency difference between the timing reference and the output of the counter. A synchronization circuit detects or receives a high-level event signal, and resets the on-going phase-frequency difference and optionally the counter to synchronize the clock output with the events.